Semiconductor device and fabrication method thereof

ABSTRACT

A semiconductor device includes a substrate having at least two fins thereon and an isolation trench between the at least two fins; and an isolation structure in the isolation trench. The isolation structure consists of a liner layer covering a lower sidewall of each of the at least two fins and a bottom surface of the isolation trench, and a stress-buffer film on the liner layer. The stress-buffer film is a silicon suboxide film of formula SiOy, wherein y&lt;2.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a division of U.S. application Ser. No. 16/451,018 filed Jun.25, 2019, which is included in its entirety herein by reference.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to the field of semiconductor processtechnology, and more particularly to a method for forming semiconductorfin structures with improved fin height profile control.

Description of the Prior Art

With increasing miniaturization of semiconductor devices, it is crucialto maintain the efficiency of miniaturized semiconductor devices in theindustry. However, as the size of the field effect transistors (FETs) iscontinuously shrunk, the development of the planar FETs faces morelimitations in the fabricating process thereof. On the other hand,nonplanar FETs, such as the fin field effect transistor (finFET) havethree-dimensional structure, not only capable of increasing the contactto the gate but also improving the controlling of the channel region,such that the nonplanar FETs have replaced the planar FETs and becomethe mainstream of the development.

The current method of forming the finFETs is forming a fin structure ona substrate primary, and then forming a gate on the fin structure. Thefin structure generally includes the stripe-shaped fin formed by etchingthe substrate. However, under the requirements of continuousminiaturization, the width of each fin, as well as the pitch betweenfins have to be shrunk accordingly. Thus, the fabricating process of thefinFETs also faces more challenges and limitations. Hence, thesemiconductor device and method of forming the same does still not fullymeet the demand of the product, and requires further improvement.

SUMMARY OF THE INVENTION

The invention provides an improved semiconductor device and amanufacturing method thereof, which can improve fin height profilecontrol and device performance.

One aspect of the invention provides a method for forming asemiconductor device is disclosed. A substrate having at least two finsthereon and an isolation trench between the at least two fins isprovided. A liner layer is then deposited on the substrate. The linerlayer conformally covers the two fins and interior surface of theisolation trench. A stress-buffer film is then deposited on the linerlayer. The stress-buffer film completely fills a lower portion that islocated at least below half of a trench depth of the isolation trench. Atrench-fill oxide layer is then deposited to completely fill an upperportion of the isolation trench.

According to some embodiment, the liner layer is a silicon oxide layerdeposited by performing an atomic layer deposition (ALD) process.

According to some embodiment, the stress-buffer film comprises amorphoussilicon.

According to some embodiment, the stress-buffer film has a thicknessthat is greater than or equal to about 40 angstroms at a fin pitch ofabout 48 nm.

According to some embodiment, the stress-buffer film has a thicknessranging between about 40 angstroms and about 80 angstroms at a fin pitchof about 48 nm.

According to some embodiment, the trench-fill oxide layer is a siliconoxide layer deposited by performing a flowable chemical vapor deposition(FCVD) process.

According to some embodiment, the method further comprises: subjectingthe trench-fill oxide layer to an anneal process.

According to some embodiment, during the anneal process, thestress-buffer film is converted to silicon suboxide film of formulaSiOy, wherein y<2.

According to some embodiment, the method further comprises: polishingthe trench-fill oxide layer, the stress-buffer film, and the liner layeruntil a top surface of the at least two fins is exposed; and recessetching the trench-fill oxide layer, the stress-buffer film, and theliner layer, thereby exposing an upper portion of the each of the atleast two fins.

Another aspect of the invention provides a semiconductor deviceincluding a substrate having at least two fins thereon and an isolationtrench between the at least two fins; and an isolation structure in theisolation trench. The isolation structure consists of a liner layercovering a lower sidewall of each of the at least two fins and a bottomsurface of the isolation trench, and a stress-buffer film on the linerlayer. The stress-buffer film is a silicon suboxide film of formulaSiOy, wherein y<2.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 are schematic diagrams illustrating a method of forming asemiconductor device according to one embodiment of the presentinvention.

DETAILED DESCRIPTION

In the following detailed description of the disclosure, reference ismade to the accompanying drawings, which form a part hereof, and inwhich is shown, by way of illustration, specific embodiments in whichthe invention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention.

Other embodiments may be utilized and structural, logical, andelectrical changes may be made without departing from the scope of thepresent invention. Therefore, the following detailed description is notto be considered as limiting, but the embodiments included herein aredefined by the scope of the accompanying claims.

FIGS. 1-4 are schematic diagrams illustrating a method of forming asemiconductor device according to one embodiment of the presentinvention. As shown in FIG. 1, a substrate 100 having multiple fins 300thereon is provided. The multiple fins 300 are separated from oneanother by isolation trenches 120 having a trench depth d. For example,the substrate 100 may include a semiconductor substrate such as asilicon containing substrate or a silicon-on-insulator (SOI) substrate.The substrate 100 may include a dense region 101 and an isolated region102. The fins 300 may be disposed in the dense region 101 and theisolated region 102 of the substrate 100 but in different pitches, asshown in FIG. 1. The pitch of the fins 300 in the dense region 101 issmaller than the pitch of the fins 300 in the isolated region 102.According to one embodiment, the fins 300 in the dense region 101 mayhave a fin pitch P of about 48 nm, which is the combination of the fincritical dimension (FCD) and the trench width W. For example, the fincritical dimension (FCD) may be 13 nm and the trench width W may be 35nm, but is not limited thereto.

According to one embodiment, the fins 300 may be formed through aself-aligned double patterning (SADP) process, such as sidewall imagetransfer (SIT) process. For example, the formation of the fins 300includes forming a plurality of mandrels (not shown in the drawings) onthe substrate 100 by using a photolithography and an etching process,performing a depositing and an etching processes sequentially to form aplurality of spacers (not shown in the drawings) at sidewalls of themandrels, using the spacers as a mask to form a patterned hard maskunderneath, and then, forming a plurality of isolation trenches 120 inthe substrate 100 to define the fins 300. However, in anotherembodiment, the formation of the fins 300 may also be accomplished byfirst forming a patterned hard mask (not shown in the drawings) on thesubstrate 100, and then performing an epitaxial process on the exposedsubstrate 100 through the patterned hard mask to form a semiconductorlayer (not shown in the drawings) such as silicon or silicon germaniumlayer to configure as corresponding fin shaped structures. A fin cutprocess (not shown in the drawings) may be performed to remove unwantedportions of the fins.

As shown in FIG. 2, the isolation trenches 120 between the fins 300 arefilled with an isolation layer 310. According to one embodiment, theisolation layer 310 includes a liner layer 311, a stress-buffer layer312 on the liner layer 311, and a trench-fill oxide layer 313 on thestress-buffer film 312. According to one embodiment, the liner layer 311is formed right after the fins 300 are formed, by depositing an oxidelayer on the substrate 100 in a blanket manner through an atomic layerdeposition (ALD) process. The liner layer 311 conformally covers thefins 300 and interior surface of the isolation trenches 120. Forexample, the liner layer 311 may be a silicon oxide layer and may have athickness of about 50˜70 angstroms, but is not limited thereto.

The stress-buffer film 312 is deposited directly on the liner layer 311.Therefore, the stress-buffer film 312 is in direct contact with theliner layer 311. The stress-buffer film 312 completely fills a lowerportion 120 b that is located at least below half of a trench depth d ofthe isolation trenches 120. For example, the stress-buffer film 312 maybe an amorphous silicon layer and may have a thickness of about 40˜80angstroms, but is not limited thereto. For example, the stress-bufferfilm 312 may have a thickness that is greater than or equal to about 40angstroms at a fin pitch P of about 48 nm. For example, thestress-buffer film 312 may have a thickness ranging between about 40angstroms and about 80 angstroms at a fin pitch P of about 48 nm.

The trench-fill oxide layer 313 is deposited directly on thestress-buffer film 312. Therefore, the trench-fill oxide layer 313 is indirect contact with the stress-buffer film 312. The trench-fill oxidelayer 313 completely fills an upper portion 120 a of each of theisolation trenches 120. According to one embodiment, the trench-filloxide layer 313 is a silicon oxide layer deposited by performing aflowable chemical vapor deposition (FCVD) process.

Subsequently, as shown in FIG. 3, an annealing process 400 is performedto anneal the trench-fill oxide layer 313. For example, the annealingprocess 400 may be performed at a temperature of about 1000° C., but isnot limited thereto. According to one embodiment, the stress-buffer film312 may be converted to silicon suboxide film of formula SiOy, whereiny<2. According to one embodiment, the trench-fill oxide layer may be asilicon oxide film of formula SiOx, wherein x<y.

As shown in FIG. 4, a planarization process (not shown in the drawings)may be performed to polish the trench-fill oxide layer 313, thestress-buffer film 312, and the liner layer 311 until the top surfacesof the fins 300 are exposed. Subsequently, the remaining trench-filloxide layer 313, the stress-buffer film 312, and the liner layer 311 arerecess etched, thereby exposing the upper portion of the each of thefins 300. The above-mentioned fin-recess process is known in the art.For example, the trench-fill oxide layer 313, the stress-buffer film312, and the liner layer 311 may be etched by using SiCoNi dry etchingprocess. In one embodiment of the present invention, the SiCoNi dryetching process primarily includes the step of reacting thefluorine-containing gas with the silicon oxide to synthesize diammoniumfluosilicate ((NH₄)₂SiF₆). In this way, the silicon oxide can beselectively removed. The aforesaid fluorine-containing gas may comprisehydrogen fluoride (HF) or nitrogen trifluoride (NF₃).

In FIG. 4, a wicking structure 320 with a height h may be definedbetween a peak adjacent to the sidewall surface of the fin 300 and alowest point of the top surface 312 a of the stress-buffer film 312 inthe dense region 101. The wicking structure 320 is formed between thefins 300 with a small pitch and covers the sidewalls of the fins 300 asshown in FIG. 4. The wicking structure 320 on the fins 300 affects theeffective height of the fins 300 and adversely affects the performanceof the semiconductor device. Therefore, it is desired to reduce theheight h of the wicking structure 320 as much as possible. The presentdisclosure addresses this issue by providing a stress-buffer film 312 inthe isolation layer 310.

It is noteworthy that in the dense region 101, only the stress-bufferfilm 312 and the liner layer 311 are left in the isolation trenches 120.Therefore, the stress-buffer film 312 and the liner layer 311 constitutethe isolation structure in each of the isolation trenches 120 in thedense region 101, while in the isolated region 102 the trench-fill oxidelayer 313, the stress-buffer film 312 and the liner layer 311 constitutethe isolation structure in each of the isolation trenches 120. Byproviding such configuration, the height h of the wicking structure 320may be reduced to about 1.74 nm in a case that the stress-buffer film312 has a thickness of about 40 angstroms at a fin pitch P of about 48nm.

Structurally, as shown in FIG. 4, a semiconductor device 1 comprises asubstrate 100 having at least two fins 300 thereon and an isolationtrench 120 between the at least two fins 300. An isolation structure 310is disposed in the isolation trench 120. The isolation structure 310consists of a liner layer 311 covering a lower sidewall of each of theat least two fins 300 and a bottom surface of the isolation trench 120,and a stress-buffer film 312 on the liner layer 311. The stress-bufferfilm 312 is a silicon suboxide film of formula SiOy, wherein y<2.

It is advantageous to use the present disclosure because the height h ofthe wicking structure can be reduced by introducing the stress-bufferfilm 312 on the liner layer 311 in the isolation trenches 120.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A semiconductor device, comprising: a substratehaving at least two fins thereon and a first isolation trench betweenthe at least two fins, wherein the first isolation trench is disposedwithin a first region; and a first isolation structure in the firstisolation trench, wherein the first isolation structure consists of aliner layer covering a lower sidewall of each of the at least two finsand a bottom surface of the first isolation trench, and a stress-bufferfilm on the liner layer, wherein the stress-buffer film is a siliconsuboxide film of formula SiOy, wherein y<2.
 2. The semiconductor deviceof claim 1 further comprising: a second isolation trench in thesubstrate within a second region; and a second isolation structure inthe second isolation trench, wherein the second isolation structurecomprising the liner layer, the stress-buffer film, and a trench-filloxide layer on the stress-buffer film.
 3. The semiconductor device ofclaim 2, wherein the first region is a dense region and the secondregion is an isolated region.
 4. The semiconductor device of claim 2,wherein a width of the second isolation trench is greater than that ofthe first isolation trench.
 5. The semiconductor device of claim 2,wherein the liner layer is a silicon dioxide layer.
 6. The semiconductordevice of claim 2, wherein the trench-fill oxide layer may be a siliconoxide film of formula SiOx, wherein x<y.
 7. The semiconductor device ofclaim 1, wherein a lower portion of the first isolation trench does notinclude the trench-fill oxide layer.
 8. The semiconductor device ofclaim 7, wherein the lower portion is located at least below half of atrench depth of the first isolation trench within the first region. 9.The semiconductor device of claim 1, wherein the stress-buffer film hasa thickness that is greater than or equal to about 40 angstroms at a finpitch of about 48 nm.
 10. The semiconductor device of claim 1, whereinthe stress-buffer film has a thickness ranging between about 40angstroms and about 80 angstroms at a fin pitch of about 48 nm.